1. Field of the Invention
The present invention relates to an input circuit and, more particularly, to an input circuit of the class which processes a given input signal to remove the noise components contained therein and to regulate the voltage level thereof, and then supplies the processed as an output signal of the input circuit to a subsequent semiconductor integrated circuit.
2. Prior Art
As indicated in FIG. 5, a prior art input circuit 1 for use in a semiconductor integrated circuit is made up of a Schmitt buffer 11, a pull-down resistance 13, and an N-channel type transistor (referred to as just "N-transistor" hereinafter) 15.
The Schmitt buffer 11 is such a buffer that has two threshold levels i.e. an upper threshold level and a lower one and varies the level of its output signal OUT depending on whether the voltage of an input signal IN exceeds the above two threshold levels, that is, whether the voltage of the input signal IN is higher than the upper threshold level or lower than the lower the threshold level. When the voltage of the input signal IN is lower than the lower threshold level, the corresponding output signal OUT is made to be a logical low level (referred to as "L-level" hereinafter), and when the voltage of the input signal IN which is higher than the upper threshold level, the corresponding output signal OUT is made to be a logical high level (referred to as "H-level" hereinafter). In the following, the above prior art input circuit will be discussed assuming that the input signal IN inputted to the first node N1 is either at the H-level or in the high impedance state (referred to as "HiZ" hereinafter).
The Schmitt buffer 11 is made up of 4 P-channel type transistors (referred to as just "P-transistor" hereinafter) 11-1, 11-3, 11-5 and 11-7, and 4 N-transistors 11-2, 11-4, 11-6 and 11-8.
Each gate of the P-transistor 11-1 and the N-transistor 11-2 is commonly connected with the first node N1 to which the input signal IN is externally inputted, and each drain of them is commonly connected with the second node N2. The source of the P-transistor 11-1 is connected with a power source VDD, and the source of the N-transistor 11-2 is connected with the ground GND.
Each gate of the P-transistor 11-3 and the N-transistor 11-4 is commonly connected with the third node N3 from which the output signal OUT is put out, and each drain of them is commonly connected with the second node N2. The source of the P-transistor 11-3 is connected with the drain of the P-transistor 11-5, and the source of the N-transistor 11-4 is connected with the drain of the N-transistor 11-6.
Each gate of the P-transistor 11-5 and the N-transistor 11-6 is commonly connected with the first node Ni. The source of the P-transistor 11-5 is connected with a power source VDD, and the source of the N-transistor 11-6 is connected with the ground GND.
Each gate of the P-transistor 11-7 and the N-transistor 11-8 is commonly connected with the second node N2, and each drain of them is commonly connected with the third node N3. The source of the P-transistor 11-7 is connected with a power source VDD, and the source of the N-transistor 11-8 is connected with the ground GND.
One end of the pull-down resistance 13 is connected with the ground GND, and the other end thereof is connected with the source of an N-transistor 15. The drain of the N-transistor 15 is connected with the first node N1. The N-transistor 15 is controlled to be turned on or off by means of a pull-down selection signal PUDN inputted to the gate thereof.
When the pull-down resistance selection signal PUDN of the H-level is inputted to the prior art input circuit 1 as made up like the above, the N-transistor 15 is turned on, so that the first node N1 is pulled down to the potential of the ground GND by the N-transistor 15 and the pull-down resistance 13. Contrary to this, when the pull-down resistance selection signal PUDN of the L-level is inputted, the N-transistor 15 is turned off, so that the first node N1 is electrically separated from the ground GND.
By the way, according to the prior art input circuit 1, however, when the pull-down resistance selection signal is at the H-level, if the H-level input signal IN is inputted to the first node N1, the current I1 is caused to flow through the N-transistor 15 and the pull-down resistance 13 as well. It is needed, therefore, to minimize such current I1 in order to achieve the reduction of electric power consumption in the input circuit 1.
Then, for meeting this need, it might be considered to electrically separate the first node N1 from the ground GND, thereby preventing the current I1 from flowing through the N-transistor 15 and the pull-down resistance 13. More specifically, for a period of time during which there is no need for the input circuit 1 to generate any output signal OUT in response to the input signal IN, in other words, a subsequent circuit of the input circuit 1 does not require any output signal OUT received thereby, if the pull-down resistance selection signal PUDN be the L-level and the N-transistor 15 be in the OFF state, the first node N1 can be electrically separated from the ground GND. With this, the current I1 can be prevented from flowing through the N-transistor 15 and the pull-down resistance 13 even if the input signal IN is at the H-level.
If, however, the input signal IN gets in the HiZ state in the condition that the first node N 1 is electrically separated from the ground GND, the first node Ni will become an unstable intermediate level, which is neither the H-level nor the L-level. In this state, both of the P-transistor 11-1 and the N-transistor 11-2 equipped in the Schmitt buffer 11 will fall into the incomplete state i.e. neither ON nor OFF state, and there will be generated a so-called penetration current I2 flowing between the source of the P-transistor 11-1 and the drain of the N-transistor 11-2. This penetration current I2 is also against the reduction of electric power consumption in the input circuit 1.
The invention has been made in view of such problems as described above, and its main object is to provide an input circuit with smaller electric power consumption.